;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 2.9.0 #5416 (Feb  3 2010) (UNIX)
; This file was generated Wed May 18 20:35:32 2011
;--------------------------------------------------------
; PIC16 port for the Microchip 16-bit core micros
;--------------------------------------------------------

	.ident "SDCC version 2.9.0 #5416 [pic16 port]"
	.file	"stepper_test.c"
	list	p=18f2455
	__config 0x300000, 0xc4
	__config 0x300001, 0x3c
	__config 0x300002, 0xf7
	__config 0x300003, 0xfe
	__config 0x300005, 0xf8
	__config 0x300006, 0x9b
	__config 0x300008, 0xff
	__config 0x300009, 0xff
	__config 0x30000a, 0xff
	__config 0x30000b, 0xff
	__config 0x30000c, 0xff
	__config 0x30000d, 0xff

	radix dec

;--------------------------------------------------------
; public variables in this module
;--------------------------------------------------------
	global _enable_b
	global _enable_a
	global _stepper_cw
	global _stepper_ccw
	global _sleep_ms
	global _do_pwm
	global _out_a1
	global _out_a2
	global _out_b1
	global _out_b2
	global _duty_cycle_pattern
	global _duty_cycle_index
	global _timer_2
	global _duty_cycle
	global _main

;--------------------------------------------------------
; extern variables in this module
;--------------------------------------------------------
	extern _SPPDATAbits
	extern _SPPCFGbits
	extern _SPPEPSbits
	extern _SPPCONbits
	extern _UFRMLbits
	extern _UFRMHbits
	extern _UIRbits
	extern _UIEbits
	extern _UEIRbits
	extern _UEIEbits
	extern _USTATbits
	extern _UCONbits
	extern _UADDRbits
	extern _UCFGbits
	extern _UEP0bits
	extern _UEP1bits
	extern _UEP2bits
	extern _UEP3bits
	extern _UEP4bits
	extern _UEP5bits
	extern _UEP6bits
	extern _UEP7bits
	extern _UEP8bits
	extern _UEP9bits
	extern _UEP10bits
	extern _UEP11bits
	extern _UEP12bits
	extern _UEP13bits
	extern _UEP14bits
	extern _UEP15bits
	extern _PORTAbits
	extern _PORTBbits
	extern _PORTCbits
	extern _PORTDbits
	extern _PORTEbits
	extern _LATAbits
	extern _LATBbits
	extern _LATCbits
	extern _LATDbits
	extern _LATEbits
	extern _TRISAbits
	extern _TRISBbits
	extern _TRISCbits
	extern _TRISDbits
	extern _TRISEbits
	extern _OSCTUNEbits
	extern _PIE1bits
	extern _PIR1bits
	extern _IPR1bits
	extern _PIE2bits
	extern _PIR2bits
	extern _IPR2bits
	extern _EECON1bits
	extern _RCSTAbits
	extern _TXSTAbits
	extern _T3CONbits
	extern _CMCONbits
	extern _CVRCONbits
	extern _ECCP1ASbits
	extern _ECCP1DELbits
	extern _BAUDCONbits
	extern _CCP2CONbits
	extern _CCP1CONbits
	extern _ADCON2bits
	extern _ADCON1bits
	extern _ADCON0bits
	extern _SSPCON2bits
	extern _SSPCON1bits
	extern _SSPSTATbits
	extern _T2CONbits
	extern _T1CONbits
	extern _RCONbits
	extern _WDTCONbits
	extern _HLVDCONbits
	extern _OSCCONbits
	extern _T0CONbits
	extern _STATUSbits
	extern _FSR2Hbits
	extern _BSRbits
	extern _FSR1Hbits
	extern _FSR0Hbits
	extern _INTCON3bits
	extern _INTCON2bits
	extern _INTCONbits
	extern _TBLPTRUbits
	extern _PCLATHbits
	extern _PCLATUbits
	extern _STKPTRbits
	extern _TOSUbits
	extern _stdin
	extern _stdout
	extern _SPPDATA
	extern _SPPCFG
	extern _SPPEPS
	extern _SPPCON
	extern _UFRML
	extern _UFRMH
	extern _UIR
	extern _UIE
	extern _UEIR
	extern _UEIE
	extern _USTAT
	extern _UCON
	extern _UADDR
	extern _UCFG
	extern _UEP0
	extern _UEP1
	extern _UEP2
	extern _UEP3
	extern _UEP4
	extern _UEP5
	extern _UEP6
	extern _UEP7
	extern _UEP8
	extern _UEP9
	extern _UEP10
	extern _UEP11
	extern _UEP12
	extern _UEP13
	extern _UEP14
	extern _UEP15
	extern _PORTA
	extern _PORTB
	extern _PORTC
	extern _PORTD
	extern _PORTE
	extern _LATA
	extern _LATB
	extern _LATC
	extern _LATD
	extern _LATE
	extern _TRISA
	extern _TRISB
	extern _TRISC
	extern _TRISD
	extern _TRISE
	extern _OSCTUNE
	extern _PIE1
	extern _PIR1
	extern _IPR1
	extern _PIE2
	extern _PIR2
	extern _IPR2
	extern _EECON1
	extern _EECON2
	extern _EEDATA
	extern _EEADR
	extern _RCSTA
	extern _TXSTA
	extern _TXREG
	extern _RCREG
	extern _SPBRG
	extern _SPBRGH
	extern _T3CON
	extern _TMR3L
	extern _TMR3H
	extern _CMCON
	extern _CVRCON
	extern _ECCP1AS
	extern _ECCP1DEL
	extern _BAUDCON
	extern _CCP2CON
	extern _CCPR2L
	extern _CCPR2H
	extern _CCP1CON
	extern _CCPR1L
	extern _CCPR1H
	extern _ADCON2
	extern _ADCON1
	extern _ADCON0
	extern _ADRESL
	extern _ADRESH
	extern _SSPCON2
	extern _SSPCON1
	extern _SSPSTAT
	extern _SSPADD
	extern _SSPBUF
	extern _T2CON
	extern _PR2
	extern _TMR2
	extern _T1CON
	extern _TMR1L
	extern _TMR1H
	extern _RCON
	extern _WDTCON
	extern _HLVDCON
	extern _OSCCON
	extern _T0CON
	extern _TMR0L
	extern _TMR0H
	extern _STATUS
	extern _FSR2L
	extern _FSR2H
	extern _PLUSW2
	extern _PREINC2
	extern _POSTDEC2
	extern _POSTINC2
	extern _INDF2
	extern _BSR
	extern _FSR1L
	extern _FSR1H
	extern _PLUSW1
	extern _PREINC1
	extern _POSTDEC1
	extern _POSTINC1
	extern _INDF1
	extern _WREG
	extern _FSR0L
	extern _FSR0H
	extern _PLUSW0
	extern _PREINC0
	extern _POSTDEC0
	extern _POSTINC0
	extern _INDF0
	extern _INTCON3
	extern _INTCON2
	extern _INTCON
	extern _PRODL
	extern _PRODH
	extern _TABLAT
	extern _TBLPTRL
	extern _TBLPTRH
	extern _TBLPTRU
	extern _PCL
	extern _PCLATH
	extern _PCLATU
	extern _STKPTR
	extern _TOSL
	extern _TOSH
	extern _TOSU
	extern __divsint
	extern __mullong
;--------------------------------------------------------
;	Equates to used internal registers
;--------------------------------------------------------
STATUS	equ	0xfd8
PCLATH	equ	0xffa
PCLATU	equ	0xffb
WREG	equ	0xfe8
BSR	equ	0xfe0
FSR0L	equ	0xfe9
FSR0H	equ	0xfea
FSR1L	equ	0xfe1
FSR2L	equ	0xfd9
POSTDEC1	equ	0xfe5
PREINC1	equ	0xfe4
PLUSW2	equ	0xfdb
PRODL	equ	0xff3
PRODH	equ	0xff4


; Internal registers
.registers	udata_ovr	0x0000
r0x00	res	1
r0x01	res	1
r0x02	res	1
r0x03	res	1
r0x04	res	1
r0x05	res	1
r0x06	res	1
r0x07	res	1
r0x08	res	1
r0x09	res	1
r0x0a	res	1
r0x0b	res	1

udata_stepper_test_0	udata
_enable_a	res	1

udata_stepper_test_1	udata
_enable_b	res	1

udata_stepper_test_2	udata
_out_a1	res	1

udata_stepper_test_3	udata
_out_a2	res	1

udata_stepper_test_4	udata
_out_b1	res	1

udata_stepper_test_5	udata
_out_b2	res	1

udata_stepper_test_6	udata
_duty_cycle_pattern	res	1

udata_stepper_test_7	udata
_timer_2	res	4

udata_stepper_test_8	udata
_duty_cycle	res	1

udata_stepper_test_9	udata
_duty_cycle_index	res	1

;--------------------------------------------------------
; interrupt vector 
;--------------------------------------------------------

;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
; ; Starting pCode block for absolute section
; ;-----------------------------------------
S_stepper_test_ivec_0x1_pwm_control	code	0X000008
ivec_0x1_pwm_control:
	GOTO	_pwm_control

; ; Starting pCode block for absolute section
; ;-----------------------------------------
S_stepper_test_ivec_0x2_timer_control	code	0X000018
ivec_0x2_timer_control:
	GOTO	_timer_control

; I code from now on!
; ; Starting pCode block
S_stepper_test__main	code
_main:
	.line	24; stepper_test.c	OSCCONbits.SCS = 0x0;		// System Clock Select bits = External oscillator
	MOVF	_OSCCONbits, W
	ANDLW	0xfc
	MOVWF	_OSCCONbits
	.line	25; stepper_test.c	OSCCONbits.IRCF = 0x7;		// Internal Oscillator Frequency Select bits 8 MHz (INTOSC drives clock directly)
	MOVF	_OSCCONbits, W
	ANDLW	0x8f
	IORLW	0x70
	MOVWF	_OSCCONbits
	.line	27; stepper_test.c	UCONbits.USBEN = 0;
	BCF	_UCONbits, 3
	.line	28; stepper_test.c	UCFGbits.UTRDIS = 1;
	BSF	_UCFGbits, 3
	.line	30; stepper_test.c	TRIS_OUT_A1 = 0;			// as output
	BCF	_TRISCbits, 0
	.line	31; stepper_test.c	TRIS_OUT_A2	= 0;			// as output
	BCF	_TRISCbits, 1
	.line	32; stepper_test.c	TRIS_ENABLE_A = 0;			// as output
	BCF	_TRISBbits, 2
	.line	33; stepper_test.c	TRIS_OUT_B1	= 0;			// as output
	BCF	_TRISBbits, 1
	.line	34; stepper_test.c	TRIS_OUT_B2	= 0;			// as output
	BCF	_TRISBbits, 0
	.line	35; stepper_test.c	TRIS_ENABLE_B = 0;			// as output
	BCF	_TRISCbits, 2
	.line	37; stepper_test.c	OUT_A1 = 0;
	BCF	_PORTCbits, 0
	.line	38; stepper_test.c	OUT_A2 = 0;
	BCF	_PORTCbits, 1
	.line	39; stepper_test.c	OUT_B1 = 0;
	BCF	_PORTBbits, 1
	.line	40; stepper_test.c	OUT_B2 = 0;
	BCF	_PORTBbits, 0
	.line	41; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	42; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	BANKSEL	_out_a1
	.line	44; stepper_test.c	out_a1 = 0;
	CLRF	_out_a1, B
	BANKSEL	_out_a2
	.line	45; stepper_test.c	out_a2 = 0;
	CLRF	_out_a2, B
	BANKSEL	_out_b1
	.line	46; stepper_test.c	out_b1 = 0;
	CLRF	_out_b1, B
	BANKSEL	_out_b2
	.line	47; stepper_test.c	out_b2 = 0;
	CLRF	_out_b2, B
	BANKSEL	_duty_cycle_pattern
	.line	49; stepper_test.c	duty_cycle_pattern = 0;
	CLRF	_duty_cycle_pattern, B
	BANKSEL	_timer_2
	.line	50; stepper_test.c	timer_2 = 0;
	CLRF	_timer_2, B
	BANKSEL	(_timer_2 + 1)
	CLRF	(_timer_2 + 1), B
	BANKSEL	(_timer_2 + 2)
	CLRF	(_timer_2 + 2), B
	BANKSEL	(_timer_2 + 3)
	CLRF	(_timer_2 + 3), B
	.line	53; stepper_test.c	RCONbits.IPEN = 1;
	BSF	_RCONbits, 7
	.line	56; stepper_test.c	T0CONbits.T08BIT = 0;	// use timer0 16-bit counter
	BCF	_T0CONbits, 6
	.line	57; stepper_test.c	T0CONbits.T0CS = 0;		// internal clock source
	BCF	_T0CONbits, 5
	.line	58; stepper_test.c	T0CONbits.PSA = 1;		// disable timer0 prescaler
	BSF	_T0CONbits, 3
	.line	59; stepper_test.c	INTCON2bits.TMR0IP = 1;	// high priority
	BSF	_INTCON2bits, 2
	.line	60; stepper_test.c	INTCONbits.TMR0IF = 1;	/* Force Instant entry to Timer 0 Interrupt */
	BSF	_INTCONbits, 2
	.line	61; stepper_test.c	T0CONbits.TMR0ON = 1;	// enable timer0
	BSF	_T0CONbits, 7
	.line	62; stepper_test.c	INTCONbits.T0IE = 1;	/* Ensure that TMR0 Interrupt is enabled    */
	BSF	_INTCONbits, 5
	.line	64; stepper_test.c	T1CONbits.T1OSCEN = 0;	// dont put t1 on pin
	BCF	_T1CONbits, 3
	.line	67; stepper_test.c	T2CONbits.T2CKPS0 = 1;
	BSF	_T2CONbits, 0
	.line	68; stepper_test.c	T2CONbits.T2CKPS1 = 0;
	BCF	_T2CONbits, 1
	.line	69; stepper_test.c	T2CONbits.TOUTPS0 = 1;
	BSF	_T2CONbits, 3
	.line	70; stepper_test.c	T2CONbits.TOUTPS1 = 0;
	BCF	_T2CONbits, 4
	.line	71; stepper_test.c	T2CONbits.TOUTPS2 = 0;
	BCF	_T2CONbits, 5
	.line	72; stepper_test.c	T2CONbits.TOUTPS3 = 1;
	BSF	_T2CONbits, 6
	.line	73; stepper_test.c	IPR1bits.TMR2IP = 0;		// low priority
	BCF	_IPR1bits, 1
	.line	74; stepper_test.c	PIR1bits.TMR2IF = 1;
	BSF	_PIR1bits, 1
	.line	75; stepper_test.c	T2CONbits.TMR2ON = 1;
	BSF	_T2CONbits, 2
	.line	76; stepper_test.c	PIE1bits.TMR2IE = 1;
	BSF	_PIE1bits, 1
	.line	78; stepper_test.c	INTCONbits.PEIE = 1;
	BSF	_INTCONbits, 6
	.line	79; stepper_test.c	INTCONbits.GIE = 1;
	BSF	_INTCONbits, 7
	.line	81; stepper_test.c	sleep_ms(100);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x64
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	83; stepper_test.c	i = MIN_SPEED;
	MOVLW	0xd0
	MOVWF	r0x00
_00105_DS_:
	.line	85; stepper_test.c	while (i < MAX_SPEED) {
	MOVLW	0xff
	SUBWF	r0x00, W
	BC	_00107_DS_
; ;multiply lit val:0x50 by variable r0x00 and store in r0x01
; ;Unrolled 8 X 8 multiplication
; ;FIXME: the function does not support result==WREG
	.line	86; stepper_test.c	stepper_cw(1, i, 20 + (80 * i / 255));
	MOVF	r0x00, W
	MULLW	0x50
	MOVFF	PRODL, r0x01
	MOVFF	PRODH, r0x02
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	CALL	__divsint
	MOVWF	r0x01
	MOVFF	PRODL, r0x02
	MOVLW	0x04
	ADDWF	FSR1L, F
	MOVLW	0x14
	ADDWF	r0x01, F
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_stepper_cw
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	87; stepper_test.c	i++;
	INCF	r0x00, F
	BRA	_00105_DS_
; ;multiply lit val:0x50 by variable r0x00 and store in r0x01
; ;Unrolled 8 X 8 multiplication
; ;FIXME: the function does not support result==WREG
_00107_DS_:
	.line	89; stepper_test.c	stepper_cw(48, i, 20 + (80 * i / 255));
	MOVF	r0x00, W
	MULLW	0x50
	MOVFF	PRODL, r0x01
	MOVFF	PRODH, r0x02
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	CALL	__divsint
	MOVWF	r0x03
	MOVFF	PRODL, r0x04
	MOVLW	0x04
	ADDWF	FSR1L, F
	MOVLW	0x14
	ADDWF	r0x03, F
	MOVF	r0x03, W
	MOVWF	POSTDEC1
	MOVF	r0x00, W
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x30
	MOVWF	POSTDEC1
	CALL	_stepper_cw
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	90; stepper_test.c	while (i > MIN_SPEED) {
	MOVFF	r0x00, r0x03
_00108_DS_:
	MOVLW	0xd1
	SUBWF	r0x03, W
	BTFSS	STATUS, 0
	BRA	_00105_DS_
	.line	91; stepper_test.c	stepper_cw(1, i, 20 + (80 * i / 255));
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	CALL	__divsint
	MOVWF	r0x04
	MOVFF	PRODL, r0x05
	MOVLW	0x04
	ADDWF	FSR1L, F
	MOVLW	0x14
	ADDWF	r0x04, F
	MOVF	r0x04, W
	MOVWF	POSTDEC1
	MOVF	r0x03, W
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_stepper_cw
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	92; stepper_test.c	i--;
	MOVLW	0xb0
	ADDWF	r0x01, F
	BTFSS	STATUS, 0
	DECF	r0x02, F
	DECF	r0x03, F
	MOVFF	r0x03, r0x00
	BRA	_00108_DS_
	RETURN	

; ; Starting pCode block
S_stepper_test__do_pwm	code
_do_pwm:
	.line	238; stepper_test.c	void do_pwm() {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	.line	244; stepper_test.c	pattern = 0;
	CLRF	r0x00
; ;multiply lit val:0x08 by variable _duty_cycle and store in r0x01
; ;Unrolled 8 X 8 multiplication
; ;FIXME: the function does not support result==WREG
	BANKSEL	_duty_cycle
	.line	245; stepper_test.c	num_on_bits = (8 * duty_cycle / 100);
	MOVF	_duty_cycle, W, B
	MULLW	0x08
	MOVFF	PRODL, r0x01
	MOVFF	PRODH, r0x02
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x64
	MOVWF	POSTDEC1
	MOVF	r0x02, W
	MOVWF	POSTDEC1
	MOVF	r0x01, W
	MOVWF	POSTDEC1
	CALL	__divsint
	MOVWF	r0x01
	MOVFF	PRODL, r0x02
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	246; stepper_test.c	for (i = 0; i < num_on_bits; i++) {
	CLRF	r0x02
_00196_DS_:
	MOVF	r0x01, W
	SUBWF	r0x02, W
	BC	_00199_DS_
	.line	247; stepper_test.c	pattern |= 1 << i;
	MOVLW	0x01
	MOVWF	r0x03
	MOVF	r0x02, W
	BZ	_00211_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00212_DS_:
	RLCF	r0x03, F
	ADDLW	0x01
	BNC	_00212_DS_
_00211_DS_:
	MOVF	r0x03, W
	IORWF	r0x00, F
	.line	246; stepper_test.c	for (i = 0; i < num_on_bits; i++) {
	INCF	r0x02, F
	BRA	_00196_DS_
_00199_DS_:
	BANKSEL	_duty_cycle_pattern
	.line	251; stepper_test.c	if (duty_cycle_pattern != pattern) {
	MOVF	_duty_cycle_pattern, W, B
	XORWF	r0x00, W
	BZ	_00183_DS_
	.line	252; stepper_test.c	duty_cycle_pattern = pattern;
	MOVFF	r0x00, _duty_cycle_pattern
	BANKSEL	_duty_cycle_index
	.line	253; stepper_test.c	duty_cycle_index = 0;
	CLRF	_duty_cycle_index, B
_00183_DS_:
	;	VOLATILE READ - BEGIN
	BANKSEL	_duty_cycle_index
	MOVF	_duty_cycle_index, W, B
	;	VOLATILE READ - END
	MOVLW	0x01
	MOVWF	r0x00
	MOVLW	0x00
	MOVWF	r0x01
	BANKSEL	_duty_cycle_index
	MOVF	_duty_cycle_index, W, B
	BZ	_00216_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00217_DS_:
	RLCF	r0x00, F
	RLCF	r0x01, F
	ADDLW	0x01
	BNC	_00217_DS_
_00216_DS_:
	MOVFF	_duty_cycle_pattern, r0x02
	CLRF	r0x03
	MOVF	r0x02, W
	ANDWF	r0x00, F
	MOVF	r0x03, W
	ANDWF	r0x01, F
	BANKSEL	_duty_cycle_index
	MOVF	_duty_cycle_index, W, B
	BZ	_00219_DS_
	NEGF	WREG
	BCF	STATUS, 0
_00220_DS_:
	BTFSC	r0x01, 7
	BSF	STATUS, 0
	RRCF	r0x01, F
	RRCF	r0x00, F
	ADDLW	0x01
	BNC	_00220_DS_
_00219_DS_:
	BANKSEL	_out_a1
	.line	258; stepper_test.c	if (out_a1 > 0) {
	MOVF	_out_a1, W, B
	BZ	_00185_DS_
	.line	259; stepper_test.c	OUT_A1 = bit;
	MOVF	r0x00, W
	ANDLW	0x01
	MOVWF	PRODH
	MOVF	_PORTCbits, W
	ANDLW	0xfe
	IORWF	PRODH, W
	MOVWF	_PORTCbits
	BRA	_00186_DS_
_00185_DS_:
	.line	262; stepper_test.c	OUT_A1 = 0;
	BCF	_PORTCbits, 0
_00186_DS_:
	BANKSEL	_out_a2
	.line	265; stepper_test.c	if (out_a2 > 0) {
	MOVF	_out_a2, W, B
	BZ	_00188_DS_
	.line	266; stepper_test.c	OUT_A2 = bit;
	MOVF	r0x00, W
	ANDLW	0x01
	RLNCF	WREG, W
	MOVWF	PRODH
	MOVF	_PORTCbits, W
	ANDLW	0xfd
	IORWF	PRODH, W
	MOVWF	_PORTCbits
	BRA	_00189_DS_
_00188_DS_:
	.line	269; stepper_test.c	OUT_A2 = 0;
	BCF	_PORTCbits, 1
_00189_DS_:
	BANKSEL	_out_b1
	.line	272; stepper_test.c	if (out_b1 > 0) {
	MOVF	_out_b1, W, B
	BZ	_00191_DS_
	.line	273; stepper_test.c	OUT_B1 = bit;
	MOVF	r0x00, W
	ANDLW	0x01
	RLNCF	WREG, W
	MOVWF	PRODH
	MOVF	_PORTBbits, W
	ANDLW	0xfd
	IORWF	PRODH, W
	MOVWF	_PORTBbits
	BRA	_00192_DS_
_00191_DS_:
	.line	276; stepper_test.c	OUT_B1 = 0;
	BCF	_PORTBbits, 1
_00192_DS_:
	BANKSEL	_out_b2
	.line	279; stepper_test.c	if (out_b2 > 0) {
	MOVF	_out_b2, W, B
	BZ	_00194_DS_
	.line	280; stepper_test.c	OUT_B2 = bit;
	MOVF	r0x00, W
	ANDLW	0x01
	MOVWF	PRODH
	MOVF	_PORTBbits, W
	ANDLW	0xfe
	IORWF	PRODH, W
	MOVWF	_PORTBbits
	BRA	_00195_DS_
_00194_DS_:
	.line	283; stepper_test.c	OUT_B2 = 0;
	BCF	_PORTBbits, 0
_00195_DS_:
	BANKSEL	_duty_cycle_index
	.line	285; stepper_test.c	duty_cycle_index++;
	INCF	_duty_cycle_index, F, B
	.line	286; stepper_test.c	duty_cycle_index &= 0x7;	// 00000111
	MOVLW	0x07
	BANKSEL	_duty_cycle_index
	ANDWF	_duty_cycle_index, F, B
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_stepper_test__timer_control	code
_timer_control:
	.line	230; stepper_test.c	static void timer_control(void) __interrupt 2 {
	MOVFF	WREG, POSTDEC1
	MOVFF	STATUS, POSTDEC1
	MOVFF	BSR, POSTDEC1
	MOVFF	PRODL, POSTDEC1
	MOVFF	PRODH, POSTDEC1
	MOVFF	FSR0L, POSTDEC1
	MOVFF	FSR0H, POSTDEC1
	MOVFF	PCLATH, POSTDEC1
	MOVFF	PCLATU, POSTDEC1
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	.line	231; stepper_test.c	if (PIR1bits.TMR2IF) {
	BTFSS	_PIR1bits, 1
	BRA	_00177_DS_
	.line	232; stepper_test.c	PR2 = TIMER2_RELOAD;		// 1 ms delay at 8 MHz
	MOVLW	0x7c
	MOVWF	_PR2
	.line	233; stepper_test.c	PIR1bits.TMR2IF = 0;
	BCF	_PIR1bits, 1
	BANKSEL	_timer_2
	.line	234; stepper_test.c	timer_2++;
	INCF	_timer_2, F, B
	BNC	_10182_DS_
	BANKSEL	(_timer_2 + 1)
	INCF	(_timer_2 + 1), F, B
_10182_DS_:
	BNC	_20183_DS_
	BANKSEL	(_timer_2 + 2)
	INCF	(_timer_2 + 2), F, B
_20183_DS_:
	BNC	_30184_DS_
	BANKSEL	(_timer_2 + 3)
	INCF	(_timer_2 + 3), F, B
_30184_DS_:
_00177_DS_:
	MOVFF	PREINC1, FSR2L
	MOVFF	PREINC1, PCLATU
	MOVFF	PREINC1, PCLATH
	MOVFF	PREINC1, FSR0H
	MOVFF	PREINC1, FSR0L
	MOVFF	PREINC1, PRODH
	MOVFF	PREINC1, PRODL
	MOVFF	PREINC1, BSR
	MOVFF	PREINC1, STATUS
	MOVFF	PREINC1, WREG
	RETFIE	

; ; Starting pCode block
S_stepper_test__pwm_control	code
_pwm_control:
	.line	221; stepper_test.c	static void pwm_control(void) __interrupt 1 {
	MOVFF	WREG, POSTDEC1
	MOVFF	STATUS, POSTDEC1
	MOVFF	BSR, POSTDEC1
	MOVFF	PRODL, POSTDEC1
	MOVFF	PRODH, POSTDEC1
	MOVFF	FSR0L, POSTDEC1
	MOVFF	FSR0H, POSTDEC1
	MOVFF	PCLATH, POSTDEC1
	MOVFF	PCLATU, POSTDEC1
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	.line	222; stepper_test.c	if (INTCONbits.TMR0IF) {	// 416,6 us delay at 20 MHz
	BTFSS	_INTCONbits, 2
	BRA	_00170_DS_
	.line	223; stepper_test.c	TMR0H = (unsigned char)(TIMER0_RELOAD >> 8);
	MOVLW	0xfb
	MOVWF	_TMR0H
	.line	224; stepper_test.c	TMR0L = (unsigned char)TIMER0_RELOAD;	/* Reload the Timer ASAP */
	MOVLW	0xff
	MOVWF	_TMR0L
	.line	225; stepper_test.c	INTCONbits.TMR0IF = 0;	/* Clear the Timer Flag  */
	BCF	_INTCONbits, 2
	.line	226; stepper_test.c	do_pwm();
	CALL	_do_pwm
_00170_DS_:
	MOVFF	PREINC1, FSR2L
	MOVFF	PREINC1, PCLATU
	MOVFF	PREINC1, PCLATH
	MOVFF	PREINC1, FSR0H
	MOVFF	PREINC1, FSR0L
	MOVFF	PREINC1, PRODH
	MOVFF	PREINC1, PRODL
	MOVFF	PREINC1, BSR
	MOVFF	PREINC1, STATUS
	MOVFF	PREINC1, WREG
	RETFIE	

; ; Starting pCode block
S_stepper_test__sleep_ms	code
_sleep_ms:
	.line	209; stepper_test.c	void sleep_ms(unsigned long ms) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVFF	r0x09, POSTDEC1
	MOVFF	r0x0a, POSTDEC1
	MOVFF	r0x0b, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, r0x03
	.line	212; stepper_test.c	start_timer_2 = timer_2;
	MOVFF	_timer_2, r0x04
	MOVFF	(_timer_2 + 1), r0x05
	MOVFF	(_timer_2 + 2), r0x06
	MOVFF	(_timer_2 + 3), r0x07
_00154_DS_:
	.line	216; stepper_test.c	while ( (((signed long)(timer_2 - start_timer_2) < 0) ? (-1 * (timer_2 - start_timer_2)) : (timer_2 - start_timer_2)) < ms) {
	MOVF	r0x04, W
	BANKSEL	_timer_2
	SUBWF	_timer_2, W, B
	MOVWF	r0x08
	MOVF	r0x05, W
	BANKSEL	(_timer_2 + 1)
	SUBWFB	(_timer_2 + 1), W, B
	MOVWF	r0x09
	MOVF	r0x06, W
	BANKSEL	(_timer_2 + 2)
	SUBWFB	(_timer_2 + 2), W, B
	MOVWF	r0x0a
	MOVF	r0x07, W
	BANKSEL	(_timer_2 + 3)
	SUBWFB	(_timer_2 + 3), W, B
	MOVWF	r0x0b
	BSF	STATUS, 0
	BTFSS	r0x0b, 7
	BCF	STATUS, 0
	BNC	_00159_DS_
	MOVF	r0x04, W
	BANKSEL	_timer_2
	SUBWF	_timer_2, W, B
	MOVWF	r0x08
	MOVF	r0x05, W
	BANKSEL	(_timer_2 + 1)
	SUBWFB	(_timer_2 + 1), W, B
	MOVWF	r0x09
	MOVF	r0x06, W
	BANKSEL	(_timer_2 + 2)
	SUBWFB	(_timer_2 + 2), W, B
	MOVWF	r0x0a
	MOVF	r0x07, W
	BANKSEL	(_timer_2 + 3)
	SUBWFB	(_timer_2 + 3), W, B
	MOVWF	r0x0b
	MOVF	r0x0b, W
	MOVWF	POSTDEC1
	MOVF	r0x0a, W
	MOVWF	POSTDEC1
	MOVF	r0x09, W
	MOVWF	POSTDEC1
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	MOVLW	0xff
	MOVWF	POSTDEC1
	CALL	__mullong
	MOVWF	r0x08
	MOVFF	PRODL, r0x09
	MOVFF	PRODH, r0x0a
	MOVFF	FSR0L, r0x0b
	MOVLW	0x08
	ADDWF	FSR1L, F
	BRA	_00160_DS_
_00159_DS_:
	MOVF	r0x04, W
	BANKSEL	_timer_2
	SUBWF	_timer_2, W, B
	MOVWF	r0x08
	MOVF	r0x05, W
	BANKSEL	(_timer_2 + 1)
	SUBWFB	(_timer_2 + 1), W, B
	MOVWF	r0x09
	MOVF	r0x06, W
	BANKSEL	(_timer_2 + 2)
	SUBWFB	(_timer_2 + 2), W, B
	MOVWF	r0x0a
	MOVF	r0x07, W
	BANKSEL	(_timer_2 + 3)
	SUBWFB	(_timer_2 + 3), W, B
	MOVWF	r0x0b
_00160_DS_:
	MOVF	r0x03, W
	SUBWF	r0x0b, W
	BNZ	_00163_DS_
	MOVF	r0x02, W
	SUBWF	r0x0a, W
	BNZ	_00163_DS_
	MOVF	r0x01, W
	SUBWF	r0x09, W
	BNZ	_00163_DS_
	MOVF	r0x00, W
	SUBWF	r0x08, W
_00163_DS_:
	BTFSS	STATUS, 0
	BRA	_00154_DS_
	MOVFF	PREINC1, r0x0b
	MOVFF	PREINC1, r0x0a
	MOVFF	PREINC1, r0x09
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_stepper_test__stepper_ccw	code
_stepper_ccw:
	.line	153; stepper_test.c	void stepper_ccw(unsigned int steps, unsigned char speed, unsigned char duty) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, _duty_cycle
	.line	156; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	157; stepper_test.c	for (i = 0; i < steps; i++) {
	CLRF	r0x03
	CLRF	r0x04
_00140_DS_:
	MOVF	r0x01, W
	SUBWF	r0x04, W
	BNZ	_00149_DS_
	MOVF	r0x00, W
	SUBWF	r0x03, W
_00149_DS_:
	BTFSC	STATUS, 0
	BRA	_00143_DS_
	.line	158; stepper_test.c	ENABLE_A = 1;
	BSF	_PORTBbits, 2
	.line	159; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	160; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	161; stepper_test.c	out_a1 = 1;
	MOVLW	0x01
	BANKSEL	_out_a1
	MOVWF	_out_a1, B
	BANKSEL	_out_a2
	.line	162; stepper_test.c	out_a2 = 0;
	CLRF	_out_a2, B
	.line	163; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	164; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	165; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVFF	r0x02, r0x05
	CLRF	r0x06
	MOVF	r0x05, W
	SUBLW	0x0d
	MOVWF	r0x05
	MOVLW	0x01
	SUBFWB	r0x06, F
	CLRF	WREG
	BTFSC	r0x06, 7
	MOVLW	0xff
	MOVWF	r0x07
	MOVWF	r0x08
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	166; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	167; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	168; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	170; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	171; stepper_test.c	ENABLE_B = 1;
	BSF	_PORTCbits, 2
	.line	172; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	BANKSEL	_out_b1
	.line	173; stepper_test.c	out_b1 = 0;
	CLRF	_out_b1, B
	.line	174; stepper_test.c	out_b2 = 1;
	MOVLW	0x01
	BANKSEL	_out_b2
	MOVWF	_out_b2, B
	.line	175; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	176; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	177; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	178; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	179; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	180; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	182; stepper_test.c	ENABLE_A = 1;
	BSF	_PORTBbits, 2
	.line	183; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	184; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	BANKSEL	_out_a1
	.line	185; stepper_test.c	out_a1 = 0;
	CLRF	_out_a1, B
	.line	186; stepper_test.c	out_a2 = 1;
	MOVLW	0x01
	BANKSEL	_out_a2
	MOVWF	_out_a2, B
	.line	187; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	188; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	189; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	190; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	191; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	192; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	194; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	195; stepper_test.c	ENABLE_B = 1;
	BSF	_PORTCbits, 2
	.line	196; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	197; stepper_test.c	out_b1 = 1;
	MOVLW	0x01
	BANKSEL	_out_b1
	MOVWF	_out_b1, B
	BANKSEL	_out_b2
	.line	198; stepper_test.c	out_b2 = 0;
	CLRF	_out_b2, B
	.line	199; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	200; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	201; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	202; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	203; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	204; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	157; stepper_test.c	for (i = 0; i < steps; i++) {
	INCF	r0x03, F
	BTFSC	STATUS, 0
	INCF	r0x04, F
	BRA	_00140_DS_
_00143_DS_:
	.line	206; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	

; ; Starting pCode block
S_stepper_test__stepper_cw	code
_stepper_cw:
	.line	97; stepper_test.c	void stepper_cw(unsigned int steps, unsigned char speed, unsigned char duty) {
	MOVFF	FSR2L, POSTDEC1
	MOVFF	FSR1L, FSR2L
	MOVFF	r0x00, POSTDEC1
	MOVFF	r0x01, POSTDEC1
	MOVFF	r0x02, POSTDEC1
	MOVFF	r0x03, POSTDEC1
	MOVFF	r0x04, POSTDEC1
	MOVFF	r0x05, POSTDEC1
	MOVFF	r0x06, POSTDEC1
	MOVFF	r0x07, POSTDEC1
	MOVFF	r0x08, POSTDEC1
	MOVLW	0x02
	MOVFF	PLUSW2, r0x00
	MOVLW	0x03
	MOVFF	PLUSW2, r0x01
	MOVLW	0x04
	MOVFF	PLUSW2, r0x02
	MOVLW	0x05
	MOVFF	PLUSW2, _duty_cycle
	.line	100; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	101; stepper_test.c	for (i = 0; i < steps; i++) {
	CLRF	r0x03
	CLRF	r0x04
_00126_DS_:
	MOVF	r0x01, W
	SUBWF	r0x04, W
	BNZ	_00135_DS_
	MOVF	r0x00, W
	SUBWF	r0x03, W
_00135_DS_:
	BTFSC	STATUS, 0
	BRA	_00129_DS_
	.line	102; stepper_test.c	ENABLE_A = 1;
	BSF	_PORTBbits, 2
	.line	103; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	104; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	105; stepper_test.c	out_a1 = 1;
	MOVLW	0x01
	BANKSEL	_out_a1
	MOVWF	_out_a1, B
	BANKSEL	_out_a2
	.line	106; stepper_test.c	out_a2 = 0;
	CLRF	_out_a2, B
	.line	107; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	108; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	109; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVFF	r0x02, r0x05
	CLRF	r0x06
	MOVF	r0x05, W
	SUBLW	0x0d
	MOVWF	r0x05
	MOVLW	0x01
	SUBFWB	r0x06, F
	CLRF	WREG
	BTFSC	r0x06, 7
	MOVLW	0xff
	MOVWF	r0x07
	MOVWF	r0x08
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	110; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	111; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	112; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	114; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	115; stepper_test.c	ENABLE_B = 1;
	BSF	_PORTCbits, 2
	.line	116; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	.line	117; stepper_test.c	out_b1 = 1;
	MOVLW	0x01
	BANKSEL	_out_b1
	MOVWF	_out_b1, B
	BANKSEL	_out_b2
	.line	118; stepper_test.c	out_b2 = 0;
	CLRF	_out_b2, B
	.line	119; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	120; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	121; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	122; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	123; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	124; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	126; stepper_test.c	ENABLE_A = 1;
	BSF	_PORTBbits, 2
	.line	127; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	128; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	BANKSEL	_out_a1
	.line	129; stepper_test.c	out_a1 = 0;
	CLRF	_out_a1, B
	.line	130; stepper_test.c	out_a2 = 1;
	MOVLW	0x01
	BANKSEL	_out_a2
	MOVWF	_out_a2, B
	.line	131; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	132; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	133; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	134; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	135; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	136; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	138; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	139; stepper_test.c	ENABLE_B = 1;
	BSF	_PORTCbits, 2
	.line	140; stepper_test.c	INTCONbits.T0IE = 0;
	BCF	_INTCONbits, 5
	BANKSEL	_out_b1
	.line	141; stepper_test.c	out_b1 = 0;
	CLRF	_out_b1, B
	.line	142; stepper_test.c	out_b2 = 1;
	MOVLW	0x01
	BANKSEL	_out_b2
	MOVWF	_out_b2, B
	.line	143; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	.line	144; stepper_test.c	INTCONbits.TMR0IF = 1;
	BSF	_INTCONbits, 2
	.line	145; stepper_test.c	sleep_ms(0xff - speed + ON_TIME);
	MOVF	r0x08, W
	MOVWF	POSTDEC1
	MOVF	r0x07, W
	MOVWF	POSTDEC1
	MOVF	r0x06, W
	MOVWF	POSTDEC1
	MOVF	r0x05, W
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	146; stepper_test.c	ENABLE_A = 0;
	BCF	_PORTBbits, 2
	.line	147; stepper_test.c	ENABLE_B = 0;
	BCF	_PORTCbits, 2
	.line	148; stepper_test.c	sleep_ms(OFF_TIME);
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x00
	MOVWF	POSTDEC1
	MOVLW	0x01
	MOVWF	POSTDEC1
	CALL	_sleep_ms
	MOVLW	0x04
	ADDWF	FSR1L, F
	.line	101; stepper_test.c	for (i = 0; i < steps; i++) {
	INCF	r0x03, F
	BTFSC	STATUS, 0
	INCF	r0x04, F
	BRA	_00126_DS_
_00129_DS_:
	.line	150; stepper_test.c	INTCONbits.T0IE = 1;
	BSF	_INTCONbits, 5
	MOVFF	PREINC1, r0x08
	MOVFF	PREINC1, r0x07
	MOVFF	PREINC1, r0x06
	MOVFF	PREINC1, r0x05
	MOVFF	PREINC1, r0x04
	MOVFF	PREINC1, r0x03
	MOVFF	PREINC1, r0x02
	MOVFF	PREINC1, r0x01
	MOVFF	PREINC1, r0x00
	MOVFF	PREINC1, FSR2L
	RETURN	



; Statistics:
; code size:	 2178 (0x0882) bytes ( 1.66%)
;           	 1089 (0x0441) words
; udata size:	   13 (0x000d) bytes ( 0.73%)
; access size:	   12 (0x000c) bytes


	end
